1. Field of the Invention
The present invention relates generally to techniques for allocating a number of cache memory banks, and, more particularly, to techniques for varying the number of memory banks utilized as cache memory and employing one or more memory banks as non-cache or local memory for a given application.
2. Relevant Background
Power consumption and operating speed constraints of central processing units (CPUs) including digital signal processors (DSPs) may limit the overall performance of mobile devices. Processing units may utilize banked memory to improve access time to data co-resident on the same integrated circuit as the processing unit thereby reducing the length of data and instruction paths to the data, which other wise may be stored farther from the processing unit. In such approaches, the number of banks in banked memory may be fixed at design time. Banked memory may be used for caching recently used instructions, data, or both. Alternatively, banked memory may also be used for fast local memory access, e.g. cache. However, once a function for bank memory is chosen at design time, the chosen function of banked memory becomes fixed.
Some conventional approaches to banked cache memory are limited in that the number of banks reserved for cache memory commonly equals a power of two. An address tag, which is used to compare against a cache tag in the banked memory, is commonly composed of bits extracted from an incoming address field and thus the number of entries a tag can select, or tag space, is a power of two. For example, one conventional approach utilizes eight banks of memory for its cache memory. Together, the eight banks are configured as an eight-way associative cache, meaning that an incoming address will cause eight cache tags, one cache tag in each bank, to be compared against the address tag carried in the incoming address. The data output of each bank is then multiplexed to select the correct bank based on the bank with the matching cache tag.
In this conventional approach, each cache access causes comparators to be enabled in each of the eight banks and the tag space can specify every cache line in the cache memory. In such an approach, reuse of one of the eight banks for other purposes is commonly not done because the tag space would not fully map to associated cache lines, potentially resulting in cache misses. Thus, simply reducing the number of banks allocated to a cache and remapping the remaining banks for another type of usage may increase power consumption and reduces the effectiveness of the cache.
Another conventional approach to banked cache memory may involve extracting one or more bits from an incoming tag to select a particular bank. Due to the extracted bits used to select a particular bank, this approach also commonly defines the number of banks in the cache to be a power of two. For example, if four banks are used, two bits are extracted from the incoming tag to specify a particular bank. For example, bit value 00 may indicate bank I, bit value 01 may indicate bank II, bit value 10 may indicate bank III, and bit value 11 may indicate bank IV. Once the two bits are extracted from the incoming tag, the particular bank for cache access is thus selected.
Where this approach is adapted for use with three banks, two bits would still be needed to specify a particular bank and two of the four values would indicate the same bank. As a result, the mapping of two values to the same bank would commonly cause the same bank to be selected twice as often as the other two banks, which can result in cache conflicts and an uneven distribution of cache data among the memory banks.